Setup: Infineon CoolSiC JFET Evaluation Board User Guide

Content

Overview

The CoolSiC JFET Evaluation Board is a high-voltage test platform for assessing Infineon CoolSiC JFET performance in solid-state circuit breaker applications. It is designed for developers, researchers, and power electronics engineers who are already trained to work safely with high-voltage equipment.

This evaluation kit is built around a two-board architecture: a baseboard that generates supplies and control signals, and a DUT board that carries the power devices and gate drivers. The board is intended for laboratory evaluation, not as a complete solid-state breaker reference design.

Specifications

Product family: CoolSiC JFET evaluation board
Board versions: EVAL_IJCQ75J1BB and EVAL_IJCQ120J1BB
Device classes: 750 V and 1200 V CoolSiC JFETs
Package type: Q-DPAK
Typical RDS(on) values: 1.61 mΩ for the 750 V device, 2.3 mΩ for the 1200 V device
Supply input: 24 V on the baseboard
Baseboard input current limit: 500 mA
Input signal level: 0/5 V
Maximum AC RMS voltage: 250 Vrms for the 750 V board, 440 Vrms for the 1200 V board
Maximum DC voltage with switches open and MOV installed: 320 VDC for the 750 V board, 585 VDC for the 1200 V board
Maximum DC voltage with switches open and no clamping elements: 400 VDC for the 750 V board, 800 VDC for the 1200 V board
Maximum current, single pulse: 716 A
Maximum inductive energy: 345 J at 2 ms for the 750 V version, 710 J at 2 ms for the 1200 V version
Isolation: 5.7 kV RMS gate-driver isolation
Switching topology: bi-directional common-source back-to-back configuration
Switch count: up to four devices with corresponding gate drivers
Paralleling support: up to two Q-DPAK devices

Detailed description

The CoolSiC JFET Evaluation Board is built to study switching behavior in SSCB-style applications, especially how the device behaves during pulse stress, inductive clamping, and fast dv/dt events. The power stage uses a common-source anti-series arrangement so the board can support blocking in both DC and AC operating modes.

The baseboard creates the low-voltage logic supply, the isolated output supply, and adjustable driver rails for the DUT board. It uses an LDO for the 5 V logic side, an isolated DC-DC stage for galvanically isolated power, and linear regulators to generate the adjustable gate-drive rails. This allows the same platform to support normally-on JFETs as well as other supported switch types.

The DUT board uses Infineon EiceDRIVER compact isolated gate drivers and includes an active Miller clamp path to limit unwanted turn-on during steep voltage transitions. The clamp FET is timed through an RC network so it can quickly pull the gate to the turn-off level when needed.

The kit includes the main switching devices, active gate-clamping FETs, and isolated gate-driver ICs, but it does not include the passive load modeling, sensing, control, or safety subsystems needed for a finished breaker system.

Safety

This board operates at dangerous voltage levels and must only be handled by qualified personnel. The DC link can reach up to 1000 VDC, so oscilloscope measurements require high-voltage differential probes.

After removing power, wait at least five minutes before touching the circuitry or reconnecting wires. The bus capacitors can remain charged even when LEDs are dark, so visual indicators must not be treated as proof that the board is safe.

The heat sink and device surfaces may become hot during testing, and the assembly contains ESD-sensitive parts. Correct electrostatic handling, proper installation, and careful thermal management are essential. Packing materials must also be removed before operation to avoid overheating or abnormal behavior.

Setup and operation

Initial setup

Inspect the board for shipping damage.
Confirm that the mounted device type matches the intended voltage class and clamping element.
Set the baseboard rails for the selected switch technology.
Apply 24 V between the baseboard 24V and AGND connectors.
Remember that the JFET is normally on, so the gate-to-source voltage must be driven to -18 V initially for JFET operation.
Feed the input pulse from the function generator into the Sig connector.
Complete the required solder bridges and jumper connections on the DUT board before testing.
Connect the baseboard and DUT board through the designated connectors.

Drive-voltage configuration

For CoolSiC JFET use, the baseboard is adjusted to roughly +2 V on the positive rail and -18 V on the negative rail. The board can also be configured for supported CoolSiC MOSFET and CoolMOS MOSFET operation by changing the rail settings according to the device type.

The baseboard includes header and resistor settings that determine the exact drive levels. For JFET evaluation, the trim settings are adjusted to the values specified for the negative and positive rails, and the DNP parts are left unpopulated or connected as required by the selected device class.

Inductive clamping test

Use an external inductor, capacitor, and HV DC supply for the inductive clamping setup. Apply a pulse at Sig, set the width to reach the desired inductor current, and capture gate-source voltage, drain-source voltage, and drain current waveforms.

During turn-off, the inductor current transfers into the MOV, which absorbs the stored magnetic energy and reduces stress on the semiconductor. This test is used to study avalanche behavior and single-pulse current handling.

dv/dt test

For dv/dt ruggedness testing, the JFET is held fully off while an external switch generates the voltage slew. The gate drivers are pulled down to the negative rail using the P3 header, and the external switch is pulsed for about 100 μs.

Raising the supply voltage changes the slew rate, allowing measurements at different dv/dt levels. Waveforms for gate-source voltage, drain-source voltage, and drain current are then recorded to check for unwanted turn-on.

Troubleshooting

If the JFET shows return-on behavior during turn-off, review the gate-clamp timing and the RC network that triggers the clamp FET.
If the gate-source waveform undershoots too far during avalanche, verify the probe setup and confirm that the waveform remains within the device limit.
If measured voltages or waveforms look unstable, check that the board is configured for the correct device class and that the right clamping element is installed.
If the board overheats or behaves abnormally, stop testing and verify that all packing materials were removed and that continuous current is not being applied beyond the intended pulse use.
If the device does not switch as expected, confirm the 24 V input supply, the Sig pulse, the jumper connections, and the solder bridges on the DUT board.

Pros & Cons

Pros: Supports 750 V and 1200 V CoolSiC JFET testing, includes isolated gate driving, handles both inductive clamping and dv/dt evaluation, and offers adjustable rails for multiple switch families.
Pros: Built-in Miller clamp and active gate protection improve behavior during fast transients.
Pros: Up to four switches and two-parallel Q-DPAK support make it useful for advanced lab experiments.
Cons: It is not a finished breaker system and lacks load-modeling, sensing, control, and safety subsystems.
Cons: Requires trained high-voltage handling and careful setup before use.
Cons: Designed for pulse testing rather than continuous current operation.

PDF

Faqs

How do I set up the CoolSiC JFET Evaluation Board before the first test?

Start by unpacking the board and checking for visible damage, then confirm that the mounted device matches the voltage class of the DUT board. Set the baseboard for the correct driver voltages, connect the 24 V auxiliary supply, and feed the input signal into the signal connector from a function generator. For JFET operation, the device must begin with a negative gate-source bias, so the off-state drive should be configured correctly before applying high voltage.

What driver voltage settings are required for CoolSiC JFET operation on this evaluation board?

For CoolSiC JFET evaluation, the board uses a bipolar drive with approximately +2 V on the positive side and about –18 V on the negative side. The baseboard trim settings must be adjusted accordingly, and the JFET should be held in the off state with the negative gate bias first. This setup is different from MOSFET use, so avoid assuming standard single-supply gate drive settings when working with the CoolSiC JFET board.

Which clamping element should be used with the 750 V or 1200 V CoolSiC JFET board?

The clamping element must match the JFET voltage class. The 750 V board uses one MOV selection, while the 1200 V board uses a higher-rated MOV part. This matters because the clamping network limits avalanche stress during inductive switching and protects the devices during turn-off. Before testing, verify that the installed clamping element matches the board version instead of mixing parts between the two voltage classes.

How is the evaluation board configured for inductive clamping tests?

For inductive clamping measurements, configure the baseboard first, then build the setup with an external power inductor, a capacitor, and an HV DC supply. Apply a pulse to the signal input and adjust the pulse width to reach the target current level in the inductor. The guide recommends capturing gate-source voltage, drain-source voltage, and drain current waveforms so you can study avalanche behavior and verify that the clamp network is working as intended.

How do I perform a dv/dt ruggedness test with the CoolSiC JFET Evaluation Board?

Set the board for JFET operation, then use the external switch in the dv/dt test setup to create the voltage slew. The guide recommends a 100 µs pulse from the function generator applied to the external switch gate, while the JFET stays fully off with about –18 V on the gate-source terminal. Increase the supply voltage step by step to create higher dv/dt levels and record VGS, VDS, and ID during the test.

Why does the board include a gate-clamping circuit, and what problem does it solve?

The gate-clamping circuit helps prevent unintended turn-on caused by the CoolSiC JFET’s Miller capacitance during fast drain-voltage transitions. Because the device can experience return-on behavior under steep dv/dt, the clamp gives the gate a low-impedance path to the off-state bias when the device is supposed to remain off. This is especially important in solid-state circuit breaker experiments, where fast transients and high switching stress are expected.

What oscilloscope and probing precautions are required when measuring this board?

Use high-voltage differential probes for voltage waveform measurements, because the board can reach very high DC-link potential during testing. Standard probe methods are not suitable for these conditions. Also remember that the LEDs going dark does not prove the capacitors are discharged, so wait the recommended discharge time before touching the circuit. Measuring the wrong way can create severe shock risk, so probe selection and safe timing are essential.

What should I check if the board does not behave correctly during testing?

First verify the board configuration, jumper and solder-bridge settings, the correct MOV selection, and the driver voltage trim positions. Make sure the external wiring matches the inductive clamping or dv/dt setup you are trying to run, and confirm that the gate is being held at the proper off-state bias for JFET operation. The guide also warns against packing material left inside the assembly, so check for anything that could cause overheating or abnormal operation.